The present invention is related to systems and methods for clocking a semiconductor device, and more particularly to systems and methods involving a multiphase clock.
Various semiconductor devices utilize a synchronous clock multiplexer circuit that allows for switching two synchronous clocks without incurring a glitch. A glitch is a high frequency pulse that may be recognized as a clock by some devices and not by others and often results in a circuit malfunction. A typical synchronous clock multiplexer utilizes one or more select signals to cause a switch between different input clocks.
Turning to FIG. 1, a prior art clock generation circuit 100 is depicted. Clock generation circuit 100 provides an ability to switch between two different clock inputs (i.e., clock 151 and clock 153) through use of a select line (i.e., select 101 and select_not 103) without incurring a glitch. An inverted version of clock 151 drives the clock inputs of data latch 113 and data latch 117, and clock 151 drives one input of a NAND gate 121. An inverted version of clock 153 drives the clock inputs of data latch 115 and data latch 119, and clock 153 drives one input of a NAND gate 123. Select 101 drives one input of an AND gate 107, and the output of data latch 117 is inverted and drives the other input of AND gate 107. Select_not 103 drives one input of an AND gate 105, and the output of data latch 119 is inverted and drives the other input of AND gate 107. The output of data latch 117 drives an input of NAND gate 121, and the output of data latch 119 drives an input of NAND gate 123. The output of NAND gate 121 and the output of NAND gate 123 drive the inputs of a NAND gate 125. NAND gate 125 drives a clock output signal 160.
In operation, clock 151 is selected to drive clock output signal 160 whenever select_not 103 is asserted high, and clock 153 is selected to drive clock output signal 160 whenever select 101 is asserted high. By feeding the output of data latch 117 back to gate select 101 and the output of data latch 119 back to gate select_not 101, any glitches on clock output signal 160 are avoided. In summary, for a selected clock to be multiplexed three steps occur sequentially: (1) select 101 and select_not 103 changes state indicating a clock multiplexing, (2) the change in select 101 and select_not 103 is clocked through respective data latches 113, 115, 117, 119 and the deselected clock is stopped, and (3) the signal that stops the clock is sampled and the selected clock enabled.
In some cases, the architecture described in FIG. 1 is extended to multiplex multiple clock phases. However, while such an extension is possible, switching between multiphase clock inputs can result in a different number of clocks being produced in one phase than in another. Where, where the multiphase clocks are used to drive differential clock inputs, the different numbers of clocks results in situation where only one side of a differential input is provided. In some cases, a different number of clocks occurring in one phase and not another may result in a circuit malfunction. In some cases, such circuit malfunctions cause irrecoverable losses of data. As one example, such a circuit may produce a misalignment in data pipes for a given design when a switch between clocks occurs. To avoid such a malfunction, the relevant pipes must be emptied and refilled. Such a process is time consuming and undesirable.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for circuit clocking.